1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device equipped with a transistor having a stacked gate structure and serving as a memory cell, and more particularly to a data latch circuit such as a defective address latch circuit provided in a redundancy circuit for storing defective addresses, or a redundancy signature circuit provided on a chip for informing the user of whether or not redundancy has been effected in the chip.
2. Description of the Related Art
In accordance with the increases in the memory capacity of a semiconductor memory devices, provision of a redundancy circuit has become indispensable in order to enhance the yield of production. The redundancy circuit, in general, has spare memory cells for compensating for a defective bit in the memory cell array, and a spare decoder consisting of a programmable address decoder with a fuse element group. The spare decoder is used to select one of the spare memory cells in place of a defective bit or memory cell. The spare programmable address decoder has defective address latch circuits for storing defective addresses. Each of the defective address latch circuits is provided for a corresponding one of address signals to be decoded. These circuits must be constructed such that stored data will not be lost even if the memory device is turned off or if the memory device is subjected to stress.
A fuse circuit applicable to part of a defective address latch circuit is disclosed in, for example, U.S. Pat. No. 4,621,346. The defective address latch circuit can be formed by connecting a selector circuit to the output node of the disclosed fuse circuit. The selector circuit outputs an address signal of 1-bit or the inverted signal of the address signal in accordance with whether or not the fuse employed in the fuse circuit has blown. Where one defective address latch circuit constructed as above is provided for each of the address signals to be decoded, and a fuse (or fuses) is selectively blown in accordance with defective address data, a corresponding defective address latch circuit (or circuits) outputs a signal of, for example, "H" level at the time of the defective address data being input, and a redundancy row or column line is selected on the basis of the output signal.
A laser fuse made of polysilicon or aluminum, which can be blown, generally by a laser beam, is used as the fuse of the defective address latch circuit.
In a non-volatile semiconductor memory device such as an EPROM (Erasable Programmable Read Only Memory), a non-volatile memory cell (hereinafter called an "EPROM" cell) can be used in place of the laser fuse. A circuit of this type is described in U.S. Pat. No. 4,803,659.
At the time of writing data into an EPROM, 0 V is applied to the source and substrate, and a high voltage is applied to the drain and control gate. As a result, an on-current flows between the drain and source, giving rise to a hot electron and a hot hole in the vicinity of the drain. The hole flows through the substrate as a substrate current, and the hot electron is injected into the floating gate, thereby increasing the threshold voltage of the EPROM cell and terminating the writing of data. Where the threshold voltage of the EPROM cell at the time of terminating of writing is sufficiently higher than a power source voltage used at the time of reading out data, and if the power source voltage is applied to the control gate of the EPROM cell during normal operation, the EPROM cell assumes the off-state or the on-state in accordance with whether it is in the writing or non-writing state, respectively. The off- and on-states of the EPROM cell can have the same function as the blown-state/non-blown-state of the laser fuse.
where an EPROM cell is used in place of a laser fuse, writing for redundancy can be effected also when die-sort testing is made to a chip formed in a wafer, thereby reducing the number of die-sort tests required to be performed (i.e., the number of occasions of contact of a testing probe with a pad). Further, it is advantageous that redundancy can be performed in the chip even after it is packaged.
To cause an EPROM cell to assume the off-state, the amount of writing in the cell must be larger than a predetermined value (i.e., the amount of a change in the threshold voltage of the cell must be larger than a predetermined value). To cause the EPROM to assume the on-state, the cell current must be large. However, if the writing amount is not so large, the following problems may occur:
Though the power source voltage of an EPROM is generally 5 V.+-.10%, 6.25.+-.0.25 V is required in order to verify writing. In such a case, 6.5 V at most is applied to the control gate of the EPROM cell at the time of reading performed for verification. In addition, when the power supply voltage contains noise, as much as 8 V may momentarily be applied to the control gate of the cell during operation thereof. In such a case, even if the EPROM cell is in the writing state, a standby current will flow if the amount of writing is not sufficient, which may adversely affect a CMOS integrated circuit employing such EPROM cells. This is because elimination of the standby current is generally required in the CMOS circuit. In the worst case, the latched data is inverted, causing malfunction of the circuit.
Moreover, the reliability of the EPROM cell may be reduced as a result of data retention. Specifically, the threshold voltage of the EPROM cell in the writing state is reduced during operation a long period of time. The larger the amount of writing in the initial state, the greater the amount of reduction of the threshold voltage.
To prevent generation of the standby current, the writing amount must be determined so as to set the threshold voltage V.sub.TH of the EPROM cell in the writing state, to a predetermined value higher than 6.5 V. However, the larger the writing amount, the greater the amount of reduction of the threshold voltage as a result of data retention.
In summary, therefore, it is difficult to determine the writing amount in the EPROM cell so as to avoid the above-described disadvantages.